SoC Platforms

Pre-built SoC design with RISC-V subsystem and peripherals

User Design Area

Up to 15mm² of die space with a standard I/O ring

Configurable IO

38 fully-configurable I/Os supporting both digital and analog signaling

Predesigned Packaging

Option of 100 QFN-packaged parts or Bare Die

Evaluation Board

Plug and play development board with software support

Open-source or Commercial EDA Tool Support

Includes complete RTL-to-GDSII open-source design flow